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“Barcelona” Processor Feature: SSE Misaligned Access
We all crave high performing code and in the process we try hard to optimize the algorithms, reorder instructions, unroll loops, avoid branches, reduce pointer usage to allow compilers to optimize, replace dynamic allocation with static allocation where the size … Continue reading
We Left Our Hearts in Barcelona
AMD Developer Outreach had a big, shiny presence at the recent Microsoft® TechEd Developers 2007 event, which took place in Barcelona, Spain during the week of November 5th (see photo montage, below). We enjoyed meeting all of the delegates who … Continue reading
¡Live from Barcelona!
While you are working hard on your next project, the Developer Outreach team is also working hard in Barcelona talking about all the great tools and techniques we have for optimizing your code for quad-core processors (and of course we’re … Continue reading
“Barcelona” Processor Feature: Advanced Bit Manipulation (ABM)
One of the new instruction sets introduced in the Third Generation AMD OpteronTM processor is Advanced Bit Manipulation (ABM), comprising two instructions that operate on general purpose registers: LZCNT and POPCNT. We’ll first explore what POPCNT can do for you. … Continue reading
“Barcelona” Processor Feature: 128-bit FPU
The new AMD “Barcelona” processors introduce dramatically improved numerical performance when using the standard SSE, SSE2 and SSE3 instruction extensions. Previous AMD processors typically could execute a vectorized SSE instruction (for example, MULPS to perform four multiplies) every two clock … Continue reading
“Barcelona” Processor Feature: Sideband Stack Optimizer
Sideband Stack Optimizer is one of many of the AMD “Barcelona” processor’s evolutionary “CPU Core IPC improvement” features. The Sideband Stack Optimizer is special circuitry in the core that tracks the value that the stack-pointer (RSP) assumes, allowing parallel execution … Continue reading
“Barcelona” Processor Feature: SSE4a Instruction Set
Writing SIMD code poses several complications. Doing 2 to 16 operations with one instruction is a powerful feature, but unless you have enough support instructions to get your data back and forth between the registers and memory, you may not … Continue reading
“Barcelona” Processor Feature: MONITOR/MWAIT
MONITOR and MWAIT are two separate instructions that are used together to monitor a range of linear memory. MONITOR tells the processor what address range to watch for a STORE instruction. MWAIT hints to the processor that it may enter … Continue reading
“Barcelona” Processor Feature: Instruction-Based Sampling (IBS)
Instruction-Based Sampling (IBS) is a performance monitoring technique that provides precise information about AMD64 instruction fetch behavior and about the execution of operations that are issued from AMD64 instructions. This information can be used to analyze and improve the performance … Continue reading
“Barcelona” Processor Feature: CPUID
To use or not to use CPUID, that is the question. CPUID is an instruction that tells you what features of a processor are supported. This instruction definitely has a time and place to be used and not to be … Continue reading
