AMD Talks-Up "Llano" x86 Innovation at ISSCC
Welcome to our first blog solely dedicated to regular contributions on Fusion. Here we plan to both define the larger Fusion strategy as it pertains to AMD’s overall engagement in the industry, as well as provide regular updates on the resulting hardware and software innovations. Today we’re talking hardware, specifically x86 power management enhancements on the first product in AMD’s Fusion family of processors.
At AMD, we live by the mantra that the Future is Fusion and our global engineering teams are working aggressively to deliver the industry’s first accelerated processing unit (APU) in support of it. That said, the consumer trends that led AMD to embark toward developing APUs began years ago; the idea wasn’t born in either a CPU or a GPU, but was born in how consumers began using their PCs. Things like: streaming video, immersive gaming, 3D user interfaces, enhanced multimedia and other compute intensive tasks became the norm rather than the exception. As an engineer, my job is to help figure out how the nuts and bolts can best fit together to help improve the user’s experience; our team is presenting today at the International Solid State Circuits Conference (ISSCC) in San Francisco some of the results of those efforts.
Let me first take a step back and recap how the first AMD APU, codenamed “Llano,” is expected to look when it enters the market:
- Four CPU cores, DDR3 memory and a DirectX® 11 capable SIMD engine integrated on-die.
- “Llano” is scheduled to be the first design from AMD using 32nm SOI process technology
- AMD plans to launch “Llano” in 2011
- This APU is expected to first appear within the forthcoming “Sabine” platform for mainstream notebooks
The AMD paper at ISSCC is specifically about some important power management enhancements made to the x86 cores on “Llano” to increase performance per-watt and help make the CPU/GPU combination even more compelling. Without diving too deep into the technical details, these innovations include:
- Core power gating – a feature of the processor that disconnects power to the core when it’s not in use, helping to reduce overall power consumption and extend battery life. AMD’s SOI process allows us to use more efficient NFET transistors for power gating as opposed to the PFET transistors used with a bulk silicon manufacturing process. In addition, AMD uses the actual chip package to re-distribute the gated ground rather than an additional thick metal layer used by other gating schemes. In total, this equates to a greater than 90% estimated reduction in leakage power.
- Digital APM Module – Measuring core power consumption is extremely important for a processor to understand how hot it’s running and when performance can be increased within a thermal constraint. There are two schools of thought here: measure temperature and amps via analog methods, or measure power consumption digitally. The former is subject to a variety of environmental issues (temperature in the room, dust on the fan, etc.), while the latter is more accurate and repeatable. AMD has implemented a digital power management technique that allows us to measure power consumption more accurately, thus helping to optimize performance-per-watt in real-time.
- De-Populated Clock Grid – Clock gating is a technique where the clock signal is combined with a control signal to either enable or disable the clock for certain parts of the circuit. This helps save power by effectively shutting down portions of a digital circuit when they are not in use and is used extensively in AMD’s x86 core. An effective way to get this clock signal to every part of a chip that needs it, with the lowest skew, is a metal grid. In a large microprocessor, the power used to drive the clock signal can be over 30% of the total power used by the entire chip. We’ve been able to dramatically reduce the amount of metal and buffering in this system to reduce clock switching power by an estimated factor of 2.
And just to show how real it all is, the picture below shows the core’s more than 35 million transistors that fit within 9.69mm2 (not counting the 1MB of L2 cache shown on the right):
I’m very pleased we are highlighting these x86 innovations from AMD and the underlying technologies that are designed to make AMD’s Fusion processors shine as “Llano” gets closer every day.
What are your thoughts on Fusion?
Samuel Naffziger, Senior Fellow, AMD
Samuel Naffziger is a senior fellow at AMD. His postings are his own opinions and may not represent AMD’s positions, strategies or opinions. Links to third party sites are provided for convenience and unless explicitly stated, AMD is not responsible for the contents of such linked sites and no endorsement is implied.
I appreciate the fact that you are sharing some cool power stuff, but this obviously is not going to keep Intel from kicking your butt in the 32nm market with its Westmere CPUs already selling. Where’s Bulldozer that we were promised in 2009?
Yeah, as i’m sure you know, that roadmap was adjusted quite some time ago, and Bulldozer was moved to 32nm, and makes much more sense. But if you didn’t know that, sell your site and go pump some gas somewhere, you sniveling pissant drone!
Kyle, there will be a number of updates in this blog about our APU development and roadmaps; power features in the x86 cores is just the first. We plan to sample x86 “Bulldozer” based products to AMD customers in the first half of this year, with launch in 2011.
I’m yet to see any Intel’s 32nm chip kicking butt of AMD’s 45nm counterpart from similar price segment.
When I think of bulldozer this quote from Tolkien’s LOTR crosses my mind:
“A wizard is never late, nor is he early, he arrives precisely when he means”
Yeah if someone asked me the codename for new chip should nave been Gandalf
but, legal department would probably freaked out 
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Thanks for the information. Intel already started to sold their i3 series processors with integrated GPU. Why AMD is so late ? I hope the GPU will be powerfull enough. Waiting for the “Llano” for the Desktop platform.
Thanks for your comment. We plan to deliver a DX11 capable GPU on a single piece of 32nm silicon; we are not putting a rehashed IGP from one process technology node and a CPU from another in an MCM package.
I am curious, will the APM information be available through AMD’s Overdrive/3rd party applications, or is it strictly being implemented as an engineering tool?
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It’s back in the future,dude.
We need honest feedback and we collectively need to keep each other honest of the reality of the marketplace and the actions of our competitors to raise the bar. We also as an entity need to understand when dynamics in the market change, we need to change also.
This is a pivotal time for AMD. If we fail to make money, Wall Street will punish us and AMD’s real options for future business will be limited.
We need to sell the heck out of what we have. Get the new stuff out the door as fast as possible and hope the market wants our output.
Ladies and Gentlemen, I know most of were able to get Calculus. Let’s try to express ourselves with better language.
We have been through tough times and things have not gone AMD’s way. The downside of risk is holding a losing hand. Let’s turn the cards we are holding now into a winning hand. Success is up to us.
I always have supported AMD, I have been waiting for the next major breakthrough. To be honest, alot of us do not see the justification to repurchase equipment when we still have dual or quad cores 2+ years old. Right now AMD is winning the pricing game which is a great advantage. However both major companies have not released anything to the general population (not nerd) that is a new milestone in technology. I’m hoping we see such future products in the future.
Right now we have a game of at and mouse, however its much more tom and jerry. Intel makes quad core, then AMD… amd says they will get bigger MB cache sizes, then intel does. Amd lowers their prices, Intel tries to catch up etc.
Intel’s gpu on a cpu, looks like its still going to be a low-performing gpu. AMD has the power of ATI, why not quadruple, or 8x give performance of a cpu+gpu, rather than a new mobile gpu thats 4 years behind or a new cpu thats on par of intel. I’d like to see a company leap past the competition rather than release products that nudge performance a little further each year.
It’s great to see AMD getting so agressive about power management on the CPU side. With the RV870 series (sorry) it seems like you’ve become the technological leader in the power space for discrete GPU’s, and depending on what Intel has waiting with Sandy Bridge you could get leadership here as well.
I have a couple of questions, though:
1) Atom competitor? At a stretch, a cut-down Llano could work in a nettop or netbook. It’s pretty clear that Stars will slaughter Pineview in terms of performance – is this an application that is workable from AMD’s point of view? I’m envisioning a 12W Llano that drives something akin to an iPad. With 32nm SOI DX11 graphics this would be a killer part, far superior to the alternatives on the market (Tegra, misc ARM and Atom). It would also position AMD excellently for leadership in the ‘performance tablet’ space that Apple has created. I’ve seen figures for per core dissipation at 2W to 2.5W – what is the dissipation for the rest of the chip (I’m guessing 7.5-10W) (meaning uncore and IGP)? Is there any chance there might be further ‘on-chipping’ of platform functions to make this a cross-application competitor in the performance embedded market? (My personal fantasy is a OoO AMD64 multi-core in a tablet like device).
2) Implementation. I’ve been agressively seeking out information on how you manage to connect the GPU with the CPU’s instruction stream – and on what level that will happen. Given that it’s 2010 and we still haven’t heard anything, my guess is that it’s all going to be in software (OpenCL/DirectCompute) but I was holding out hope for something more significant that might further alter the programming model for the platform (a la AMD64). If you can’t say anything about how this will be done, is there a timeline on which that information might become available?
3) AVX (alright, I almost made it through the whole post without a question about Bulldozer). Has this situation changed at all? I know Intel took the rather classless position of dumping their AVX implementation after you guys had already ‘agreed’ to follow their lead (which benefits them) – is AMD still planning to use Intel’s AVX 1.0 (compared with the revised AVX)? Are the new AVX extensions going to play a role at all in Fusion?
Not everyone is as unimpressed with your achievements on Llano as Kyle is – a full quad-core implemenation at sub 25W is extremely impressive and a technical achievement to be proud of – your competitor is certainly nowhere near that with their technology.
Thanks for the information!
ATi GPUs have been great in the last two generations, most bang for the buck.
However, software is the problem.
If I own a (currently) inferior nVidia card, I can have some PhysiX fun and use it in several CUDA applications.
Try to promote the Bullet Engine or at least make 100% sure that your OpenCL drivers will be next to perfect. These will be crucial.
The fastest Ferrarri is useless on a bumpy country road.
Good luck in any case, I see the potential, I hope it could be used in 2011
Alexander, you are right: the development of an ecosystem of developer tools for our Fusion family of APUs is a game changer. We’ll discuss those developer related updates in this blog too, as well as directing people over to http://developer.amd.com and the growing OpenCL and DirectCompute communities.
i hope this delay doesn’t equate to the same mistake AMD made when it tried to delay and launch a native quad-core CPU (Barcelona) instead of Intel’s double dual-core (2 die x 2 dual = quad) approach
although Intel launched a MCM GPU on the CPU package, they still have another year to improve and prevent overtaking before Fusion, or Llano, launches
but still, i will be betting my wallet on Fusion
sure hope to see some big performance ‘leaps’ with it, not the usual tiny ‘steps’
thanks
Mannor,
Our development of our first APUs “Llano” and “Ontario” remains on track per our public guidance. There is at least one obvious difference between our competitor’s approach and AMD’s: “Llano” for example will include DX11 support with GPU compute capability. We’ll share more details on our approach in the months ahead.
AMD Senior Engineers like Mr.Naffziger have better things to do instead of wasting their precious time arguing with clueless fanboys. Dont waste his time, and our time, with your nonsensical thoughts. Go play with your Intel machines, you have what you want.
no L3 cache?
maybe the performance will drop down..
Congratulations on the new Power Gating techniques on Llano, i bet that those will be introduced in all of the 2011 AMD products, Bulldozer/Bobcat etc…When will the GPU details on Llano will be revealed?, Shaders,ROPS,Full DirectCompute 5.0/DX11 Capabilities, the Memory Controller that feeds the beast, the connection between the CPU cores and the GPU etc…
Thanks funtactic. More details to come in the months ahead; we’ll be sure to talk about any new information on our first APUs here in the blog.
Can you talk about SDK’s?
I think the one with the best SDK wins. Best in terms of how easy it is to write a game or app that utilizes the APU.
Will there be Open Source Linux SDK support? I know that AMD is working hard to open source drivers for Evergreen.
Louise, AMD provides the ATI Stream Software Development Kit (SDK), a complete development platform created by AMD to allow you to quickly and easily develop applications that utilize the compute capabilities of both the CPU and GPU. The SDK allows you to develop your applications in a high-level language, OpenCL (Open Computing Language) which is an open and royalty-free programming standard for general-purpose computations on heterogeneous systems. OpenCL allows programmers to preserve their expensive source code investment and easily target both multi-core CPUs and the latest GPUs, such as those from AMD. OpenCL can be used in either linux or windows environments. See http://developer.amd.com/gpu/ATIStreamSDK/Pages/default.aspx.
Um just a question… People are a bit worried about it… How much bandwidth should the igpu in fusion receive? I mean it has to be a bit much bigger than 20GB/s two way(what it should get shared with the CPU) for what amd is talking about? I’m not asking for numbers but does AMD have big surprises under it’s sleeve?
We haven’t disclosed APU bandwidth for “Llano” yet, stay tuned to this blog for more updates on APU architecture in the future.
I’m actually surprised that APU R&D is taking place in Canada, rather than the “usual” CPU research facilities… (judging from the PR you put out last week). Or is this not the case?
Also, guys, you say that it should be circa 35 million transistors for the core-sans-L2. This seems like a pretty low tranny count. Is that number accurate? Is you throw in some 25 million for the L2, the whole CPU will be about what… 60 million? Or did I misread it?
Clarkdale is currently 383 million…
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I think the revolution will be concerning price and cost. It seems that the die size of the Fusion including the graphics will be close to that of a quad core Athlon X4 (Propus) CPU. Right? Accordingly, a Fusion PC would achieve the following savings: Northbridge (10-15$), discrete graphic card (50-100$). So in terms of manufacturing costs it would be competitive even against a cheap PC with integrated graphics, but Fusion graphics will be capable to compete against much better discrete graphics (5600 series?). Moreover, Fusion PCs will have even more advantages because of smaller form factors (Mainboard, smaller chipcount etv.). This is a clear win-win-win-killer-product!